The present invention relates to a manufacturing method of a semiconductor device, and in particular, relates to a manufacturing method of a semiconductor device which includes a memory cell having a plurality of gates.
There is considered, for example, a microcomputer as a semiconductor device including a flash memory and a CPU (Central Processing Unit). For example, it is preferable that the flash memory uses a nonvolatile memory which is an element in which recorded information remains when power is shut down. By mounting the nonvolatile memory and a logic semiconductor device over the same semiconductor substrate in a mixed state, it is possible to form a microcomputer having a high performance. The microcomputer in which mounts the nonvolatile memory and the logic semiconductor device are arranged is used widely for industrial machines, home appliances, car-mounted apparatuses, and the like.
Generally, the nonvolatile memory included in the microcomputer stores a program necessary for the microcomputer and is used for optional read-out of the program. Therefore, it is preferable to use the microcomputer which mounts the nonvolatile memory and the logic semiconductor device in a mixed state. An example for a memory cell structure of such a nonvolatile memory which is suitable for the mixed mounting with the logic semiconductor device includes a memory cell having a sprit gate structure in which a control MIS (Metal Insulator Semiconductor) transistor and a storage MIS transistor are formed in an integrated manner.
Among the memory cells having the split gate structures, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory cell using MONOS for the storage MIS transistor is disclosed in, for example, Japanese Patent Laid-Open No. 2011-29631 (Patent Document 1).
Meanwhile, since realization of a thinner gate insulating film has been limited recently in the MIS transistor, a structure obtained by using a high dielectric constant insulating film (so-called, high-k film) for the gate insulating film and using a metal film as a gate electrode is disclosed in Japanese Patent Laid-Open No. 2011-49282 (Patent Document 2), for example.
Furthermore, for the MONOS-type memory cell, a structure in which the storage MIS transistor is formed in a side wall part of the control MIS transistor is disclosed in Japanese Patent Laid-Open No. 2010-282987 (Patent Document 3), for example.